Introduction & Overview

5G RAN virtualization involves CU (Centralized Unit) and DU (Distributed Unit) virtualization. The hardware platform is in general a COTS server with NIC and hardware accelerators, where needed. Especially in compute-heavy scenarios, hardware deployments can significantly accelerate any open RAN implementation and raw performance, reducing the number of CPU cores required and power consumption. Looking at the architecture for layer 1 acceleration, there are two fundamental approaches – look-aside acceleration and inline acceleration. The principal difference between them is that in look-aside acceleration, only selected functions are sent to the accelerator, and then back to the CPU, while in inline acceleration parts of or the whole data flow and functions are sent through the accelerator. For higher bandwidth open RAN applications, full L1 processing offload may be required. In this case, an inline hardware accelerator is likely to deliver the best results with lowest latency and minimum cores required. The PAC-01x series is the world’s 1st ASIC-based PCIe DU solution, which leverages NXP’s Layerscape® Access family of programmable baseband processors (LA-12 series+LX-2 series) to provide multiple 25GbE eCPRI interfaces and maximum support for four 4T4R 100Mhz RRH/RU. With less OPEX and leveraging the current facility with minimal installation process, GENEViSiO’s PAC-01x card, built with powerful NXP 5G solution in PCIe x8 form factor, can be easily deployed in the existing platforms to run the O-RAN fronthaul protocols and to offload the DU function onto the host. On the other hand, the PAC-01x could work seamlessly with the CU in the MEC servers for the lower layer split (LLS) to ensure the quality of the ultra- low latency as well as the bandwidth. With the different software configuration to support high-PHY offload or full DU/REC offload , memory expansion and 1pps & GPS timing synchronization, the PAC-01x will bring more flexibility and empower the end customer with more 5G capabilities in the edge computing. Moreover, either in the Public or local 5G infrastructure, the different size of the PAC-01x series could easily fit into the existing equipment and move to the 5G with low-latency and high-speed bandwidth on the fly.

PAC-010

PAC-012

Specification

Model# PAC-010 PAC-012
Form factor Gen3 x8 / Gen3 x16 Gen3 x4
Processer NXP LX2160 NXP LX2162
5G Silicon LA1201 *2 LA1201 *1
Fronthaul ports to RU 4 x 10/25GbE SFP28 2 x 10/25GbE SFP28
Memory slot (up to 32GB/per slot) 2 x slots N/A
On-board memory N/A 16GB, ECC
IEEE 1588/SyncE ITU G.8261, G.8271, G.8272, G.8273
DU function Support Split Option 7-2 & Option 6(FAPI)
Dimension Full Height, 3/4 Length (111.15 x 241 x 17.14 mm) Half Height, Half Length (68.90 x 167.65 x 17.14 mm)
Power Consumption 75W (max.) 30W (max.)
Order Information
  • PAC-010:Gen3x8
  • PAC-010-H:Gen3x16(OTII support)
  • PAC-010-HG:Gen3x16(OTII & GNSS support)